1. Field of the Invention
The present invention relates to an information processing apparatus which incorporates a plurality of arithmetic units and a plurality of storage units, and an information processing method.
2. Description of the Related Art
In recent years, in order to implement multi-functional apparatuses, hardware components such as arithmetic devices (CPUs), main storage devices (e.g., RAMs), and auxiliary storage devices (HDDs) are incorporated in various apparatuses, and various functions are implemented by application programs.
Furthermore, a proposal that implements further multi-functions of an information processing apparatus by incorporating a plurality of arithmetic devices, and a plurality of OSs (operating systems) in one information processing apparatus has been made (for example, see Japanese Patent Laid-Open No. 2007-35066).
As the information processing apparatus has gained more multi-functions, power consumption in the information processing apparatus tends to increase. For this reason, it is required to reduce power consumption as much as possible not only in an operation mode in an active state of the information processing apparatus (non-power saving mode) but also in an operation mode in a sleep state of the apparatus (power saving mode).
On the other hand, in terms of improvement of usability, it is required to shorten an activation time from when electric power is supplied to the information processing apparatus until completion of activation, and to shorten a return time required until the apparatus returns from the power saving mode to a normal power mode.
To meet such conflicting needs, for example, Japanese Patent Laid-Open No. 2005-78197 and Japanese Patent Laid-Open No. 2007-25882 have proposed an arrangement in which electric power is supplied to only a main storage device upon transiting to the power saving mode, and main programs and required data are stored in the main storage device. With this arrangement, the return time can be shortened while reducing power consumption in the power saving mode.
Also, the following arrangement is known. That is, all data (hibernation image) on a main storage device is copied to, for example, a HDD using a given hibernation function, and the hibernation image of the main storage device is read out from the HDD when the apparatus resumes. In this case, the state of the main storage device immediately before the power supply is turned off can be restored. By applying this arrangement, power consumption in the power saving mode can be suppressed, and the return time can be shortened compared to a case in which an operating system and application software are launched from the beginning.
However, when a plurality of arithmetic devices and a plurality of main storage devices are incorporated in the information processing apparatus, the above arrangement cannot sufficiently reduce the power consumption and shorten the return time. For example, in the arrangement described in Japanese Patent Laid-Open No. 2005-78197 and Japanese Patent Laid-Open No. 2007-25882 above, in order to store main programs and required data in the power saving mode, electric power has to be supplied to the plurality of main storage devices, and power consumption in the power saving mode increases.
On the other hand, in case of the arrangement using the hibernation function, the power consumption can be suppressed, but data transfer from an auxiliary storage device to the plurality of main storage devices requires more time. Hence, shortening of the return time is limitated.